Manufacturing method of a non-volatile memory

ABSTRACT

A non-volatile memory formed on a first conductive type substrate is provided. The non-volatile memory includes a gate, a second conductive type drain region, a charge storage layer, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region is formed in the first conductive type substrate at the first side of the gate. The charge storage layer is formed on the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate at the second side of the gate. The second side is opposite to the first side.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of U.S. provisionalapplications Ser. No. 60/597,210, filed on Nov. 17, 2005 and 60/743,630,filed on Mar. 22, 2006, all disclosures are incorporated therewith.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device. Moreparticularly, the present invention relates to a non-volatile memory anda manufacturing method and an operation method thereof.

2. Description of Related Art

Electrically erasable programmable read-only memory (EEPROM) is anon-volatile memory wherein data can be written, read, or erasedrepeatedly, and the data stored in an EEPROM remains even when the powersupply is turned off. Thus, EEPROM has become broadly applied topersonal computers and other electronic apparatuses.

Presently, a non-volatile memory having a charge storage layer ofsilicon nitride is provided. Such silicon nitride charge storage layerusually has respectively a silicon oxide layer on the top and at thebottom, so as to form a memory cell ofsilicon-oxide-nitride-oxide-silicon (SONOS) structure. When voltages aresupplied to the control gate and the source region/drain regions of thedevice to program the device, hot electrons are produced in the channelregion and close to the drain region and are injected into the chargestorage layer. The electrons injected into the charge storage layer arenot distributed evenly in the entire charge storage layer, instead, theelectrons stay in a particular area in the charge storage layer andpresent Gaussian distribution in the direction of the channel, thus,leakage current won't be produced easily.

However, when fabricating a SONOS memory, the gate of a SONOS memorycell in the memory cell region and the gate of a transistor in the logiccircuit region are usually formed within the same step, and theoxide/nitride/oxide (ONO) layer of the SONOS memory cell and the gateoxide of the transistor in the logic circuit region are then patternedright after the gates are formed. However, since the thicknesses andstructures of the oxide/nitride/oxide layer of the SONOS memory cell andthe gate oxide of the transistor in the logic circuit region are verydifferent, the thickness of the gate oxide becomes thinner and thinneralong with the minimization of the device. Thus, it is very difficult tocompletely pattern the oxide/nitride/oxide layer of the SONOS memorycell and to prevent the substrate surface of the logic circuit regionfrom being over-etched and producing recess. To resolve the foregoingproblems, the SONOS memory cell in the memory cell region and thetransistor in the logic circuit region are fabricated separately, andwhich complicates the fabricating process.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to provide amanufacturing method of non-volatile memory. The structure of thenon-volatile memory is very simple, and the manufacturing processthereof is compatible with general logic circuit processes.

The present invention provides a manufacturing method of a non-volatilememory which includes following steps. First, a first conductive typesubstrate is provided and a gate is formed on the first conductive typesubstrate. A second conductive type first lightly doped region is formedin the substrate at the first side of the gate, and a charge storagelayer is formed on the sidewall of the gate. Next, a second conductivetype source region is formed in the substrate at the first side of thegate, and a second conductive type source region is formed in thesubstrate at the second side of the gate, wherein the second conductivetype first lightly doped region is formed in the first conductive typesubstrate between the second conductive type source region and the gate.

According to the manufacturing method of a non-volatile memory in anexemplary embodiment of the present invention, if the first conductivetype is P-type, the second conductive type is N-type; if the firstconductive type is N-type, the second conductive type is P-type.

According to the manufacturing method of a non-volatile memory in anexemplary embodiment of the present invention, a first dielectric layeris further formed on the first conductive type substrate before the gateis formed on the first conductive type substrate.

According to the manufacturing method of a non-volatile memory in anexemplary embodiment of the present invention, the first dielectriclayer has a first thickness at the first side and a second thickness atthe second side, and the second thickness is greater than the firstthickness.

According to the manufacturing method of a non-volatile memory in anexemplary embodiment of the present invention, a second dielectric layeris further formed on the first conductive type substrate after the gateis formed on the first conductive type substrate.

According to the manufacturing method of a non-volatile memory in anexemplary embodiment of the present invention, the steps of forming thesecond conductive type first lightly doped region in the firstconductive type substrate at the first side of the gate are asfollowing. First, a patterned photoresist layer is formed on thesubstrate, and the patterned photoresist layer exposes the firstconductive type substrate at the first side of the gate. Next, an ionimplantation process is performed to form the second conductive typefirst lightly doped region. After that, the patterned photoresist layeris removed.

According to an exemplary embodiment of the present invention, themanufacturing method of a non-volatile memory further includes forming afirst conductive type lightly doped region in the substrate at thesecond side of the gate, and the first conductive type lightly dopedregion is between the second conductive type drain region and the gate.

According to the manufacturing method of a non-volatile memory in anexemplary embodiment of the present invention, the steps of forming thesecond conductive type first lightly doped region in the firstconductive type substrate at the first side of the gate and the firstconductive type lightly doped region in the substrate at the second sideof the gate are as following. A first patterned photoresist layer isformed on the substrate, and the first patterned photoresist layerexposes the first conductive type substrate at the first side of thegate. A first ion implantation process is performed to form the secondconductive type first lightly doped region. Then, a second patternedphotoresist layer is formed on the substrate after the first patternedphotoresist layer is removed, the second patterned photoresist layerexposes the first conductive type substrate at the second side of thegate. Next, a second ion implantation process is performed to form thefirst conductive type lightly doped region. After that, the secondpatterned photoresist layer is removed.

According to an exemplary embodiment of the present invention, themanufacturing method of a non-volatile memory further includes forming asecond conductive type second lightly doped region in the substrate atthe second side of the gate, and the second conductive type secondlightly doped region is between the second conductive type drain regionand the gate.

According to the manufacturing method of a non-volatile memory in anexemplary embodiment of the present invention, the steps of forming thesecond conductive type first lightly doped region and the secondconductive type second lightly doped region in the first conductive typesubstrate at the first side and the second side of the gate and formingthe first conductive type lightly doped region in the first conductivetype substrate at the second side of the gate are as following. First, afirst ion implantation process is performed to form the secondconductive type first lightly doped region and the second conductivetype second lightly doped region. A patterned photoresist layer isformed on the first conductive type substrate, and the patternedphotoresist layer exposes the first conductive type substrate at thesecond side of the gate. The patterned photoresist layer is removedafter a second ion implantation process is performed to form the firstconductive type lightly doped region.

According to the manufacturing method of a non-volatile memory in anexemplary embodiment of the present invention, the steps of forming thecharge storage layer on the sidewall of the gate are as following. Ananisotropic etching process is performed to remove part of the chargestorage material layer after the charge storage material layer is formedon the first conductive type substrate.

According to a non-volatile memory in the present invention, the chargestorage layer of a memory cell is formed on the sidewall of the gatestructure, which is different from the conventional technique that theoxide/nitride/oxide (ONO) layer of a silicon-oxide-nitride-oxide-silicon(SONOS) memory is formed below the gate. The structure in the presentinvention can greatly reduce the size of the device.

Moreover, the manufacturing method of non-volatile memory in the presentinvention can be integrated with a typical complementary metal-oxidesemiconductor (CMOS) manufacturing process and no photolithographyetching process of multiple masks is required, thus, the manufacturingtime of a device can be shortened.

Furthermore, in a memory cell of the present invention, a lightly dopedregion of the same conductive type as that of the source region isformed at the source, and no lightly doped region is formed at the drainor the substrate at the drain is neutralized, or even a lightly dopedregion of the inverse conductive type as that of the drain region isformed at the drain. Thus, regardless right-reading or inverse reading,the turn-on current at reading the memory cell is smaller so that thedevice can have better performance.

In order to make the aforementioned and other objects, features andadvantages of the present invention comprehensible, a preferredembodiment accompanied with figures is described in detail below.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary, and are intended toprovide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1A is a cross-sectional diagram of a non-volatile memory cellaccording to an exemplary embodiment of the present invention.

FIG. 1B is a cross-sectional diagram of a non-volatile memory cellaccording to an exemplary embodiment of the present invention.

FIG. 1C is a cross-sectional diagram of a non-volatile memory cellaccording to an exemplary embodiment of the present invention.

FIG. 1D is a cross-sectional diagram of a non-volatile memory cellaccording to an exemplary embodiment of the present invention.

FIG. 1E is a cross-sectional diagram of a non-volatile memory cellaccording to an exemplary embodiment of the present invention.

FIG. 1F is a cross-sectional diagram of a non-volatile memory cellaccording to an exemplary embodiment of the present invention.

FIG. 2A is a simplified circuit diagram of a memory cell array composedof non-volatile memory cells according to an embodiment of the presentinvention.

FIG. 2B is a cross-sectional diagram of the memory cells in the firstrow in FIG. 2A.

FIG. 3A is a simplified circuit diagram of a memory cell array composedof non-volatile memory cells according to an embodiment of the presentinvention.

FIG. 3B is a cross-sectional diagram of the memory cells in the firstrow in FIG. 3A.

FIGS. 4A˜4E are cross-sectional diagrams illustrating the manufacturingflow of a non-volatile memory according to an exemplary embodiment ofthe present invention.

FIGS. 5A˜5B are cross-sectional diagrams illustrating the manufacturingflow of a non-volatile memory according to an exemplary embodiment ofthe present invention.

FIGS. 6A˜6C are cross-sectional diagrams illustrating the manufacturingflow of a non-volatile memory according to an exemplary embodiment ofthe present invention.

FIGS. 7A˜7D are cross-sectional diagrams illustrating the manufacturingflow of a non-volatile memory according to an exemplary embodiment ofthe present invention.

FIGS. 8A˜8C and FIG. 8I are diagrams illustrating the operation of anN-type non-volatile memory.

FIGS. 8D˜8E are diagrams illustrating the operation of a P-typenon-volatile memory.

FIG. 8F is a diagram illustrating a right reading operation performed toa non-volatile memory according to an embodiment of the presentinvention.

FIG. 8G is a diagram illustrating an inverse reading operation performedto a non-volatile memory according to an embodiment of the presentinvention.

FIG. 8H is a diagram illustrating an erasing operation performed to anon-volatile memory according to an embodiment of the present invention.

DESCRIPTION OF EMBODIMENTS

FIG. 1A is a cross-sectional diagram of a non-volatile memory cellaccording to an exemplary embodiment of the present invention.

Referring to FIG. 1A, a memory cell 101 a is, for example, formed on afirst conductive type substrate 100. The first conductive type substrate100 is, for example, a silicon substrate. The memory cell is, forexample, composed of a gate dielectric layer 102, a gate 104, adielectric layer 106, charge storage layers 108 a and 108 b, a secondconductive type source region 110, a second conductive type drain region112, and a second conductive type lightly doped region 114.

The gate 104 is, for example, formed on the first conductive typesubstrate 100. The material of the gate 104 is, for example, dopedpolysilicon.

The gate dielectric layer 102 is, for example, formed between the gate104 and the first conductive type substrate 100. The material of thegate dielectric layer 102 is, for example, silicon oxide.

The second conductive type source region 110 and the second conductivetype drain region 112 is, for example, formed in the first conductivetype substrate at two sides of the gate 104.

The charge storage layers 108 a and 108 b is, for example, formed on thesidewall of the gate 104, wherein the charge storage layer 108 a isformed on the substrate between the second conductive type drain region112 and the gate 104, and the charge storage layer 108 b is formed onthe substrate between the second conductive type source region 112 andthe gate 104. In the present embodiment, only the charge storage layer108a is used for storing charges, while the charge storage layer 108 bis not for storing charge but can be considered as an insulating spacer.The material of the charge storage layers 108 a and 108 b is, forexample, silicon nitride. However, the material of the charge storagelayers 108 a and 108 b is not limited to silicon nitride but may also beother material which can trap charges, such as SiON, TaO, SrTiO₃, orHfO₂.

The second conductive type lightly doped region 114 is, for example,formed in the first conductive type substrate 100 between the gate 104and the second conductive type source region 110, namely, below thecharge storage layer 108 b.

In the embodiment described above, if the first conductive type isP-type, then the second conductive type is N-type, and the memory cellis a N-channel memory cell; if the first conductive type is N-type, thenthe second conductive type is P-type, and the memory cell is a P-channelmemory cell.

In a memory cell of the present invention, since there is no secondconductive type lightly doped region formed at the second conductivetype drain region 112, the charge storage layer 108 a can be used forstoring charges. The second conductive type lightly doped region 114 isformed at the second conductive type source region 110, and then thecharge storage layer 108 b cannot be used for storing charges. Thestructure of the memory cell in the present invention is very simple andthe manufacturing method can be integrated with a typical complimentarymetal-oxide semiconductor (CMOS) manufacturing process.

FIG. 1B is a cross-sectional diagram of a non-volatile memory cellaccording to another exemplary embodiment of the present invention. InFIG. 1B, the components same as those in FIG. 1A have the same referencenumerals and the descriptions thereof are skipped herein. Only thedifferences between the two will be described below.

Referring to FIG. 1B, the memory cell 101 b includes a first conductivetype lightly doped region 116 formed at the second conductive type drainregion 112. The first conductive type lightly doped region 116 is, forexample, formed in the first conductive type substrate 100 between thegate 104 and the second conductive type drain region 112, namely, belowthe charge storage layer 108 a.

In the memory cell 101 b shown in FIG. 1B, a lightly doped region of theconductive type inverse to that of the source/drain region is formed atthe drain, and which helps to inject carriers into the charge storagelayer 108 a.

FIG. 1C is a cross-sectional diagram of a non-volatile memory cellaccording to yet another exemplary embodiment of the present invention.In FIG. 1C, the components same as those in FIG. 1A have the samereference numerals and the descriptions thereof are skipped herein. Onlythe differences between the two will be described below.

Referring to FIG. 1C, the memory cell 101 c includes a second conductivetype lightly doped region 114 a and a first conductive type lightlydoped region 116 formed at the second conductive type drain region 112.The first conductive type lightly doped region 116 is, for example,formed in the first conductive type substrate 100 between the gate 104and the second conductive type drain region 112, namely, below thecharge storage layer 108 a. The second conductive type lightly dopedregion 114 a is, for example, formed in the first conductive typesubstrate 100 between the gate 104 and the second conductive type drainregion 112, namely below the charge storage layer 108 a.

In the memory cell 101 c shown in FIG. 1C, since a second conductivetype lightly doped region 114 a and a first conductive type lightlydoped region 116 of inverse conductive types are formed at the drain,the substrate 100 below the charge storage layer 108 a can be maintainedto the first conductive type, and which helps to inject carriers intothe charge storage layer 108 a.

FIG. 1D is a cross-sectional diagram of a non-volatile memory cellaccording to yet another exemplary embodiment of the present invention.In FIG. 1D, the components same as those in FIG. 1A have the samereference numerals and the descriptions thereof are skipped herein. Onlythe differences between the two will be described below.

Referring to FIG. 1D, the gate dielectric layer 102 a between the gate104 and the first conductive type substrate 100 has differentthicknesses at where close to the second conductive type drain region112 and the second conductive type source region 110. For example, thethickness of the gate dielectric layer 102 a at where close to thesecond conductive type source region 110 is d1, and the thickness of thegate dielectric layer 102 a at where close to the second conductive typedrain region 112 is d2, wherein d2 is greater than d1.

In the memory cell 101 d as shown in FIG. 1D, the gate dielectric layer102 a at where close to the second conductive type drain region 112 isthicker and accordingly can resist higher voltage, thus, the problem ofthe gate dielectric layer being damaged when a high voltage is suppliedto the drain can be resolved.

FIG. 1E is a cross-sectional diagram of a non-volatile memory cellaccording to yet another exemplary embodiment of the present invention.In FIG. 1E, the components same as those in FIG. 1A have the samereference numerals and the descriptions thereof are skipped herein. Onlythe differences between the two will be described below.

As shown in FIG. 1E, the memory unit 101 e is, for example, composed oftwo memory cells 101 a formed in symmetric manner. Namely, two adjacentmemory cells 101 a share a second conductive type source region 110.

Since two memory cells share one second conductive type source region110, the device integration can be increased. A memory unit 101 ecomposed of two memory cells 101 a is illustrated in FIG. 1E, however,the memory unit 101 e may also be composed of two memory cells 101 b˜101d in FIG. 1B˜FIG. 1D formed in symmetric manner.

FIG. 1F is a cross-sectional diagram of a non-volatile memory cellaccording to yet another exemplary embodiment of the present invention.In FIG. 1F, the components same as those in FIG. 1E have the samereference numerals and the descriptions thereof are skipped herein. Onlythe differences between the two will be described below.

As shown in FIG. 1F, the memory unit 101 f is, for example, composed oftwo memory cells 101 a formed in symmetric manner. However, the twomemory cells 101 a are very close to each other so that no secondconductive type source region 110 is formed, but the two memory cells101a share a second conductive type lightly doped region 114. Since nosecond conductive type source region 110 is formed between the twomemory cells 101 a, the device integration can be further increased.

In the non-volatile memory of the present invention, the charge storagelayer is formed on the sidewall of the gate structure, and which isdifferent from that the oxide/nitride/oxide (ONO) layer of aconventional SONOS memory is formed below the gate. The structure in thepresent invention can greatly reduce device size. The manufacturingprocess of the non-volatile memory in the present invention is simpleand no photolithography process of multiple masks is required,furthermore, the process can be integrated with a typical CMOS process,thus, the manufacturing time of device can be shortened. Besides, thesecond conductive type drain regions 112 in the non-volatile memories inFIGS. 1A˜1F do not have to be self aligned to the gate.

FIG. 2A is a simplified circuit diagram of a memory cell array composedof non-volatile memory cells according to an embodiment of the presentinvention. FIG. 2B is a cross-sectional diagram of the memory cells inthe first row in FIG. 2A.

As shown in FIGS. 2A and 2B, the memory cell array is, for example,composed of memory cells Q11˜Q46, a plurality of source lines SL1˜SL4, aplurality of bit lines BL1˜BL4, and a plurality of word lines WL1˜WL6.The structures of the memory cells Q11˜Q46 are as shown in FIGS. 1A˜1D.The memory cell illustrated in FIG. 1A is described as an example inFIG. 2B.

The memory cells Q11˜Q46 are arranged as an array. The memory cellsQ11˜Q16 are, for example, formed in symmetric manner in direction X (thedirection of rows). Two adjacent memory cells among memory cells Q11˜Q16share one source region S or one drain region D. For example, the memorycells Q11 and Q12 share the drain region D1, the memory cells Q13 andQ14 share the drain region D2, and the memory cells Q15 and Q16 sharethe drain region D3. The memory cells Q12 and Q13 share the sourceregion S2, and the memory cells Q14 and Q15 share the source region S3.

The source lines SL1˜SL4 are arranged in parallel in direction Y (thedirection of columns) and connect the source regions of the memory cellsin the same column. For example, the source line SL1 connects the,source regions of the memory cells Q11˜Q41, the source line SL2 connectsthe source regions of the memory cells Q12˜Q41 and the memory cellsQ13˜Q43, . . . , the source line SL4 connects the source regions of thememory cells Q16˜Q46.

The bit lines BL1˜BL4 are arranged in parallel in direction X (thedirection of rows) and connect the drain regions of the memory cells inthe same row. For example, the bit line BL1 connects the drain regionsof the memory cells Q11˜Q16, the bit line BL2 connects the drain regionsof the memory cells Q21˜Q26, . . . , the bit lines BL4 connects thedrain regions of the memory cells Q41˜Q46.

The word lines WL1˜WL6 are arranged in parallel in the direction ofcolumns and connect the gates of the memory cells in the same column.For example, the word line WL1 connects the gates of the memory cellsQ11˜Q41, the word line WL2 connects the gates of the memory cellsQ12˜Q42, . . . , the word line WL6 connects the gate of the memory cellsQ16˜Q46.

FIG. 3A is a simplified circuit diagram of a memory cell array composedof non-volatile memory cells according to another embodiment of thepresent invention. FIG. 3B is a cross-sectional diagram of the memorycells in the first row in FIG. 3A.

As shown in FIG. 3A and FIG. 3B, the memory cell array is, for example,composed of memory cells Q11˜Q46, a plurality of bit lines BL1˜BL7, anda plurality of word lines WL1˜WL6. The structures of the memory cellsQ11˜Q46 are as illustrated in FIGS. 1A˜1D. The memory cell illustratedin FIG. 1A is described as an example in FIG. 3B.

The memory cells Q11˜Q46 are arranged as an array. In direction X (thedirection of rows), the memory cells Q11˜Q16 are, for example, connectedin series, the memory cells Q21˜Q26 are, for example, connected inseries, . . . , the memory cells Q41˜Q46 are, for example, connected inseries. Here series connection refers to that the source region of amemory cell is connected to the drain region of the previous adjacentmemory cell, and the drain region of the memory cell is connected to thesource region of the next memory cell. That is, in the direction ofrows, two adjacent memory cells share one doped region S/D, and the S/Dis used as the source region of a memory cell and the drain region ofthe other memory cell.

The bit lines BL1˜BL7 are arranged in parallel in direction Y (thedirection of columns) and connect the doped regions S/D in the samecolumn. For example, the bit line BL1 connects the doped regions S/D atone side of the memory cells Q11˜Q41, the bit line BL2 connects thedoped regions S/D between the memory cells Q12˜Q42 and the memory cellsQ13˜Q42, . . . , the bit line BL6 connects the doped regions S/D betweenthe memory cells Q15˜Q45 and the memory cells Q16˜Q46, the bit line BL7connects the doped regions S/D at the other side of the memory cellsQ16˜Q46.

The word lines WL1˜WL6 are arranged in parallel in the direction of rowsand connect the gates of the memory cells in the same row. For example,the word line WL1 connects the gates of the memory cells Q11˜Q16, theword line WL2 connects the gates of the memory cells Q21˜Q26, . . . ,the word line WL4 connects the gates of the memory cells Q41˜Q46.

In a memory cell array of the present invention, the charge storagelayers of the memory cells Q11˜Q46 are formed on the sidewalls of thegates, and such structure can greatly reduce device size. Themanufacturing process is very simple and no photolithography process ofmultiple masks is required, further more, the manufacturing process canbe integrated with a typical CMOS process, so that the manufacturingtime of the device can be shortened.

Next, the manufacturing method of a non-volatile memory in the presentinvention will be described. FIGS. 4A˜4E are cross-sectional diagramsillustrating the manufacturing flow of a non-volatile memory accordingto an exemplary embodiment of the present invention.

Referring to FIG. 4A, first, a first conductive type substrate 200 isprovided and a dielectric layer 202 and a conductive layer 204 areformed on the substrate 200. The first conductive type substrate 200 is,for example, a silicon substrate. The material of the dielectric layer202 is, for example, silicon oxide, and the formation method thereof is,for example, thermal oxidation. The material of the conductive layer 204is, for example, doped polysilicon, and the formation method thereof is,for example, forming a layer of undoped polysilicon by chemical vapordeposition first and then performing ion implantation to form theconductive layer 204, or performing chemical vapor deposition within-situ dopant implantation to form the conductive layer 204.

Referring to FIG. 4B, the conductive layer 204 and the dielectric layer202 are patterned to form a gate 204a and a gate dielectric layer 202a.The method of patterning the conductive layer 204 and the dielectriclayer 202 is, for example, photolithography etching technique. Adielectric layer 206 is then formed on the substrate 200. The materialof the dielectric layer 206 is, for example, silicon oxide, and theformation method thereof is, for example, thermal oxidation or chemicalvapor deposition.

Referring to FIG. 4C, a patterned photoresist layer 208 is formed on thesubstrate 200, and the patterned photoresist layer 208 exposes thesubstrate 200 at one side of the gate 204 a. The patterned photoresistlayer 208 is, for example, formed with photolithography technique. Next,a dopant implantation step 210 is performed with the patternedphotoresist layer 208 as a mask to form a second conductive type lightlydoped region 212 in the substrate 200. The dopant implantation step 210is, for example, to implant dopants into the substrate 200 by ionimplantation.

Referring to FIG. 4D, a charge storage layer 214 is formed on thesidewall of the gate 204 after the patterned photoresist layer 208 isremoved. The material of the charge storage layer 214 is, for example,silicon nitride, SiON, TaO, SrTiO₃, or HfO₂. The formation method of thecharge storage layer 214 is, for example, forming a charge storagematerial layer by chemical vapor deposition first and then removing partof the charge storage material layer by performing an anisotropicetching process.

Referring to FIG. 4E, a dopant implantation step 216 is then performedwith the gate 204 a having the charge storage layer 214 as a mask toform a second conductive type source region 218 a and a secondconductive type drain region 218 b in the substrate 200. The dopantimplantation step 216 is, for example, to implant dopant into thesubstrate 200 by ion implantation.

FIGS. 5A˜5B are cross-sectional diagrams illustrating the manufacturingflow of a non-volatile memory according to another exemplary embodimentof the present invention. The components in FIGS. 5A˜5B same as those inFIGS. 4A˜4E have the same reference numerals and the descriptionsthereof are skipped herein.

Referring to FIG. 5A, following the steps in FIG. 4C, the patternedphotoresist layer 208 is removed after the second conductive typelightly doped region 212 is formed in the substrate 200. Next, anotherpatterned photoresist layer 220 is formed on the substrate 200, and thepatterned photoresist layer 220 exposes the substrate 200 at the otherside (the side opposite to the second conductive type lightly dopedregion 212) of the gate 204 a. The patterned photoresist layer 220 is,for example, formed with photolithography technique. After that, adopant implantation step 222 is performed with the patterned photoresistlayer 220 as a mask to form a first conductive type lightly doped region224 in the substrate 200. The dopant implantation step 222 is, forexample, to implant dopant into the substrate 200 by ion implantation.

Referring to FIG. 5B, a charge storage layer 214 is formed on thesidewall of the gate 204 after the patterned photoresist layer 220 isremoved. Then a dopant implantation step 216 is performed with the gate204 a having the charge storage layer 214 as a mask to form a secondconductive type source region 218 a and a second conductive type drainregion 218 b in the substrate 200.

FIGS. 6A˜6C are cross-sectional diagrams illustrating the manufacturingflow of a non-volatile memory according to yet another exemplaryembodiment of the present invention. The components in FIGS. 6A˜6C sameas those in FIGS. 4A˜4E have the same reference numerals and thedescriptions thereof are skipped herein.

Referring to FIG. 6A, following the steps in FIG. 4B, after the gate 204a, the gate dielectric layer 202 a, and the dielectric layer 206 areformed on the substrate 200, a dopant implantation step 225 is performedwith the gate 204 a as a mask to form second conductive type lightlydoped regions 212 a and 212 b in the substrate 200 at two sides of thegate 204 a. The dopant implantation step 225 is, for example, to implantdopant into the substrate 200 by ion implantation.

Referring to FIG. 6B, a patterned photoresist layer 226 is formed on thesubstrate 200, and the patterned photoresist layer 226 exposes thesubstrate 200 at one side of the gate 204 a. The patterned photoresistlayer 226 is, for example, formed with photolithography technique. Then,a dopant implantation step 228 is performed with the patternedphotoresist layer 226 as a mask to form a first conductive type lightlydoped region 230 in the substrate 200. The dopant implantation step 228is, for example, to implant dopant into the substrate 200 by ionimplantation.

Referring to FIG. 6C, a charge storage layer 214 is formed on thesidewall of the gate 204 after the patterned photoresist layer 226 isremoved. Then, a dopant implantation step 216 is performed with the gate204 a having the charge storage layer 214 as a mask to form a secondconductive type source region 218 a and a second conductive type drainregion 218 b in the substrate 200.

FIGS. 7A˜7D are cross-sectional diagrams illustrating the manufacturingflow of a non-volatile memory according to an exemplary embodiment ofthe present invention. The components in FIGS. 7A˜7D same as those inFIGS. 4A˜4E have the same reference numerals and the descriptionsthereof are skipped herein.

Referring to FIG. 7A, first, a first conductive type substrate 200 isprovided, and a dielectric layer 202 and a conductive layer 204 areformed on the substrate 200. The first conductive type substrate 200 is,for example, a silicon substrate. The dielectric layer 202 is, forexample, composed of a dielectric layer 201a and a dielectric layer 201b. Thus, the dielectric layer 202 has two different thicknesses. Thematerial of the dielectric layer 202 is, for example, silicon oxide. Theformation method of the dielectric layer 202 is, for example, forming adielectric layer on the substrate 200 first, then patterning thedielectric layer to form the dielectric layer 201 a, and after thatforming the dielectric layer 201 b on the substrate 200. The material ofthe conductive layer 204 is, for example, doped polysilicon, and theformation method thereof is, for example, forming a layer of undopedpolysilicon by performing chemical vapor deposition first, and thenperforming ion implantation to form the conductive layer 204, orperforming chemical vapor deposition with in-situ dopant implantation toform the conductive layer 204.

Referring to FIG. 7B, the conductive layer 204 and the dielectric layer202 are patterned to form the gate 204 a and the gate dielectric layer202 a. The method of patterning the conductive layer 204 and thedielectric layer 202 is, for example, photolithography etchingtechnique. A dielectric layer 206 is then formed on the substrate 200.The material of the dielectric layer 206 is, for example, silicon oxide,and the formation method thereof is, for example, thermal oxidation orchemical vapor deposition.

Referring to FIG. 7C a patterned photoresist layer 208 is formed on thesubstrate 200, and the patterned photoresist layer 208 exposes thesubstrate 200 at one side of the gate 204 a. The patterned photoresistlayer 208 is, for example, formed with photolithography technique. Then,a dopant implantation step 210 is performed with the patternedphotoresist layer 208 as a mask to form a second conductive type lightlydoped region 212 in the substrate 200. The second conductive typelightly doped region 212 is formed at the thinner side of the dielectriclayer 202 a. The dopant implantation step 210 is, for example, toimplant dopant into the substrate 200 by ion implantation.

Referring to FIG. 7D, a charge storage layer 214 is formed on thesidewall of the gate 204 after the patterned photoresist layer 208 isremoved. Then, a dopant implantation step 216 is performed with the gate204 a having the charge storage layer 214 as a mask to form a secondconductive type source region 218 a and a second conductive type drainregion 218 b in the substrate 200. The dopant implantation step 216 is,for example, implanting dopants into the substrate 200 by ionimplantation. The fabricating method of the lightly doped regions inFIGS. 7A˜7D may also adopt the methods described in the embodiments ofFIGS. 5A˜5B and FIGS. 6A˜6C.

According to the manufacturing method of non-volatile memory in thepresent invention, the charge storage layer is formed on the sidewall ofthe gate structure, and which is very different from the conventionaltechnique that the ONO layer of a SONOS memory is formed below the gate.Thus, the manufacturing method of non-volatile memory in the presentinvention can be integrated with a typical CMOS process and can shortenthe time required for manufacturing the device.

Next, the operation method in the present invention will be described.First, an N-channel memory cell will be described. FIGS. 8A˜8C and FIG.81 are diagrams illustrating the operation of an N-type non-volatilememory. FIGS. 8D˜8E are diagrams illustrating the operation of a P-typenon-volatile memory. In an operation with normal bias, the voltage whichallows the memory cell to have the maximum turn-on current is voltageVD, and voltage VD is, for example, about 2.5V.

The voltage levels described below comply with foregoing parameter.

As shown in FIG. 8A, a voltage V1 is supplied to the gate, whereinvoltage V1 is higher than voltage VD and which is, for example, about3˜7V. A voltage V2 is supplied to the N-type drain region, whereinvoltage V2 is 1.5˜3 times of voltage VD and which is, for example, about3˜7V. The N-type source region and the P-type substrate are grounded.Electrons are injected into the charge storage layer with channel hotelectron injection.

As shown in FIG. 8B, a voltage V3 is supplied to the gate, whereinvoltage V3 is lower than 0V and which is, for example, about −3˜7V. Avoltage V4 is supplied to the N-type drain region, wherein voltage V4 is1.5˜3 times of voltage VD lo and which is, for example, about 3˜7V. TheN-type source region is floated, and the P-type substrate is grounded.Holes are injected into the charge storage layer with band-to-bandtunneling induced hot hole injection.

As shown in FIG. 8C, a voltage V5 is supplied to the gate, whereinvoltage V5 is higher than the threshold voltage Vth of the memory celland lower than voltage VD and which is, for example, about 1V. A voltageV6 is supplied to the N-type drain region, wherein voltage V6 is 1.5˜3times of voltage VD and which is, for example, about 3˜7V. A voltage of0V is supplied to the N-type source region and the P-type substrate.Holes are injected into the charge storage layer with drain breakdowninduced hot hole injection.

As shown in FIG. 8I, a voltage V17 is supplied to the gate, whereinvoltage V17 is higher than voltage VD and which is, for example, about3˜7V. A voltage V18 is supplied to the N-type drain region, whereinvoltage V18 is 1.5˜3 times of voltage VD and which is, for example,about 3˜7V. A voltage V19 is supplied to the N-type source region andwhich is, for example, about 0˜2V. A voltage V20 is supplied to theP-type substrate and which is, for example, about 0˜−2V. Electrons areinjected into the charge storage layer with channel hot carrier inducedsecondary carrier injection.

As shown in FIG. 8D, a voltage V7 is supplied to the gate, whereinvoltage V7 is lower than the threshold voltage Vth of the memory celland which is, for example, about −3˜−7V. A voltage V8 is supplied to theP-type drain region, wherein voltage V8 is the negative of 1.5˜3 timesof voltage VD and which is, for example, about −3˜−7V. A voltage of 0Vis supplied to the P-type source region and the N-type substrate.Electrons are injected into the charge storage layer with channel hotelectron injection.

As shown in FIG. 8E, a voltage V9 is supplied to the gate, whereinvoltage V9 is higher than 0V and which is, for example, about 3˜7V. Avoltage V10 is supplied to the P-type drain region, wherein voltage V10is the negative of 1.5˜3 times of voltage VD and which is, for example,about −3˜−7V. The P-type source region is floated, and a voltage of 0Vis supplied to the N-type substrate. Electrons are injected into thecharge storage layer with band-to-band tunneling induced hot holeinjection.

Next, the reading method of the present invention will be described.FIGS. 8F and 8G illustrate the reading operation of a non-volatilememory according to an embodiment of the present invention. FIG. 8F is adiagram illustrating a right reading operation performed to anon-volatile memory according to an embodiment of the present invention,and FIG. 8G is a diagram illustrating an inverse reading operationperformed to a non-volatile memory according to an embodiment of thepresent invention.

As shown in FIG. 8F, a voltage Vr1 is supplied to the gate, whereinvoltage Vr1 is equal to voltage VD and which is, for example, about2.5V. A voltage Vr2 is supplied to the second conductive type drainregion, and voltage Vr2 is, for example, about 1V. A voltage of 0V issupplied to the second conductive type source region. In the situationdescribed above, the digital data stored in the memory cell can bedetermined by detecting the channel current in the memory cell.

As shown in FIG. 8G, a voltage Vr3 is supplied to the gate, whereinvoltage Vr3 is equal to voltage VD and which is, for example, about2.5V. A voltage Vr4 is supplied to the second conductive type sourceregion, and the voltage Vr4 is, for example, about 1V or 1.5V. A voltageVr5 is supplied to the second conductive type drain region, and thevoltage Vr5 is, for example, about 0V or 0.5V. In the situationdescribed above, the digital data stored in the memory cell can bedetermined by detecting the channel current in the memory cell.

According to the operation method of a non-volatile memory in thepresent invention, charges stored in the memory cell may also be erasedby high power radiation (for example, ultraviolet radiation) or by FNtunneling effect.

FIG. 8H is a diagram illustrating an erasing operation performed to anon-volatile memory according to an embodiment of the present invention.

As shown in FIG. 8H, when erasing the memory cell with FN tunnelingeffect, a voltage Ve1 is supplied to the gate, a voltage Ve2 is suppliedto the second conductive type drain region, and the second conductivetype source region and the first conductive type substrate is floated.Wherein the voltage difference between voltage Ve1 and voltage Ve2 mayinduce FN tunneling effect. Voltage Ve1 is about −6˜−0V, and voltage Ve2is about 3˜7V. However, voltage Ve1 may also be about 6˜10V, and voltageVe2 may also be about −3˜−7V.

According to the operation method of a non-volatile memory in thepresent invention, electrons or holes are injected into the chargestorage layer by one of channel hot electron injection, band-to-bandtunneling induced hot hole injection, drain breakdown induced hot holeinjection, and channel hot carrier induced secondary carrier injection,so as to program/erase the memory cell. Right reading or inverse readingcan be performed to the non-volatile memory in the present invention.Besides, charges stored in the memory cell may also be erased by usinghigh power radiation (for example, ultraviolet radiation) or FNtunneling effect.

Besides, in the memory cell of the present invention, a lightly dopedregion of the same conductive type as that of the source region at thesource, no lightly doped region is formed at the drain or the substrateat the drain is neutralized, or even a lightly doped region of theinverse conductive type of that of the drain region is formed at thedrain, so that at reading the memory cell, regardless right reading orinverse reading, the memory cell in the present invention has smallerturn-on current and better device performance compared to conventionalmemory cell wherein lightly doped regions of the same conductive type asthat of the source region are formed at both the source and the drain.

Next, the operations of a non-volatile memory array in the presentinvention will be described, which includes programming, erasing, anddata reading. An exemplary embodiment of the operation method of anon-volatile memory will be described below; however, the operationmethod is not limited thereto. The memory unit Q13 illustrated in FIGS.2A and 2B will be described below as an example.

Referring to both FIG. 2A and FIG. 2B, when a programming operation isperformed to the selected memory cell Q13, a voltage Vp1, for example,5V, is supplied to the selected word line WL3. A voltage Vp2, forexample, 5V, is supplied to the selected bit line BL1. The selectedsource line SL2 is grounded. The other non-selected word lines WL1˜WL2,WL4˜WL6, non-selected bit lines BL2˜BL4, and source lines SL1 andSL3˜SL4 are grounded. The selected memory cell Q13 is programmed bychannel hot electron injection.

Referring to both FIG. 2A and FIG. 2B, when an erasing operation isperformed to the selected memory cell Q13, a voltage Ve1, for example,−5V, is supplied to the selected word line WL3. A voltage Ve2, forexample, 5V, is supplied to the selected bit line BL1. The selectedsource line SL2 is floated. The other non-selected world lines WL1˜WL2,WL4˜WL6, non-selected bit lines BL2˜BL4, and source lines SL1, SL3˜SL4are grounded. The selected memory cell Q13 is erased by band-to-bandtunneling induced hot hole injection. The voltage Ve1, for example, −5V,is supplied to all the word lines WL1˜WL6, the voltage Ve2, for example,5V, is supplied to all the bit lines BL1˜BL4, and all the source linesSL2 are floating, so as to erase all the memory cells in the entiresection.

Referring to both FIG. 2A and FIG. 2B, when a reading operation isperformed to the selected memory cell Q13, a voltage Vr1, for example,2.5V, is supplied to the selected word line WL3, a voltage Vr2, forexample, 0.5V, is supplied to the selected bit line BL1, a voltage Vr3,for example, 1V, is supplied to the selected source line SL2, and theother non-selected word lines WL1˜WL2, WL4˜WL6, non-selected bit linesBL2˜BL4, and the source lines SL1, and SL3˜SL4 are grounded, so as toread the selected memory cell Q13.

In foregoing description, the operations are performed to only onememory cell in the memory cell array, however, the programming, erasing,or reading operation may also be performed to memory cells in unit ofbite, section, or block by controlling the word lines, source lines, andbit lines in a non-volatile memory array of the present invention.

The operation patterns of another non-volatile memory array in thepresent invention will be described next. The operations includeprogramming, erasing, and data reading. The memory cell Q13 illustratedin FIG. 3A and FIG. 3B will be described below as an example.

Referring to both FIG. 3A and FIG. 3B, when a programming operation isperformed to the selected memory cell Q13, a voltage Vp1, for example,5V, is supplied to the selected word line WL3. A voltage Vp2, forexample, 5V, is supplied to the selected bit line BL4 connected to thedrain of the selected memory cell Q13. The selected bit line BL3connected to the source of the selected memory cell Q13 is grounded. Avoltage Vp3, for example, 3V, is supplied to the non-selected bit linesBL5˜BL7 formed at the drain of the selected memory cell Q13 to preventthe memory cells connected to the non-selected bit lines BL5˜BL7 frombeing programmed. The other non-selected word lines WL1˜WL2, WL4˜WL6 andthe non-selected bit lines BL1˜BL2 formed at the source of the selectedmemory cell Q13 are grounded. The selected memory cell Q13 is programmedby channel hot electron injection.

Referring to both FIG. 3A and FIG. 3B, when an erasing operation isperformed to the selected memory cell Q13, a voltage Ve1, for example,−5V, is supplied to the selected word line WL3. A voltage Ve2, forexample, 5V, is supplied to the selected bit line BL4 connected to thedrain of the selected memory cell Q13. The selected bit line BL3connected to the source of the selected memory cell Q13 is floated. Avoltage Vp3, for example, 3V, is supplied to the non-selected bit linesBL5˜BL7 formed at the drain of the selected memory cell Q13 to preventthe memory cells connected to the non-selected bit lines BL5˜BL7 frombeing erased. The other non-selected word lines WL1˜WL2, WL4˜WL6 and thenon-selected bit lines BL1˜BL2 formed at the source of the selectedmemory cell Q13. The selected memory cell Q13 is erased by band-to-bandtunneling induced hot hole injection.

Referring to both FIG. 3A and FIG. 3B, when a reading operation isperformed to the selected memory cell Q13, a voltage Vr1, for example,2.5V, is supplied to the selected word line WL3. A voltage Vr2, forexample, 0.5V, is supplied to the selected bit line BL3. A voltage Vr3,for example, 1V, is supplied to the selected bit line BL4. The voltageVr2, for example, 0.5V, is supplied to the non-selected bit linesBL5˜BL7 formed at the drain of the selected memory cell Q13. The voltageVr3, for example, 1V, is supplied to the non-selected bit lines BL1˜BL2formed at the source of the selected memory cell Q13. The othernon-selected word lines WL1˜WL2 and WL4˜WL6 are grounded.

In foregoing description, the operations are performed to only onememory cell in the memory cell array, however, the programming, erasing,or reading operation may also be performed to memory cells in unit ofbite, section, or block by controlling the word lines, source lines, andbit lines in a non-volatile memory array of the present invention.

In overview, in a non-volatile memory of the present invention, thecharge storage layer of a memory cell is formed on the sidewall of thegate structure, and which is different from that in a conventionalSONOS, the ONO layer is formed below the gate. The structure in thepresent invention can greatly reduce the size of the device.

Moreover, the manufacturing method of a non-volatile memory in thepresent invention can be integrated with a typical CMOS process and nophotolithography etching process with multiple masks is required, thus,the manufacturing time of the device can be shortened.

Furthermore, according to a memory cell in the present invention, alightly doped region of the same conductive type as that of the sourceregion is formed at the source and no lightly doped region is formed atthe drain or the substrate at the drain is neutralized, or even alightly doped region of the inverse conductive type as that of the drainregion is formed at the drain, thus, regardless right reading or inversereading, the turn-on current at reading the memory cell is smaller, sothat better device performance can be achieved.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

1. A manufacturing method of a non-volatile memory, the manufacturingmethod comprising: providing a first conductive type substrate; forminga gate on the first conductive type substrate; forming a secondconductive type first lightly doped region in the substrate at a firstside of the gate; forming a charge storage layer on the sidewall of thegate; and forming a second conductive type source region in thesubstrate at the first side of the gate, and forming a second conductivetype drain region in the substrate at a second side of the gate, whereinthe second conductive type first lightly doped region is formed in thefirst conductive type substrate between the second conductive typesource region and the gate.
 2. The manufacturing method as claimed inclaim 1, wherein if the first conductive type is P-type, then secondconductive type is N-type; if the first conductive type is N-type, thesecond conductive type is P-type.
 3. The manufacturing method as claimedin claim 1, further comprising forming a first dielectric layer on thefirst conductive type substrate before forming the gate on the firstconductive type substrate.
 4. The manufacturing method as claimed inclaim 3, wherein the first dielectric layer has a first thickness at thefirst side and a second thickness at the second side, and the secondthickness is greater than the first thickness.
 5. The manufacturingmethod as claimed in claim 1, further comprising forming a seconddielectric layer on the first conductive type substrate after formingthe gate on the first conductive type substrate.
 6. The manufacturingmethod as claimed in claim 1, wherein the step of forming the secondconductive type first lightly doped region in the first conductive typesubstrate at the first side of the gate comprises: forming a patternedphotoresist layer on the substrate, the patterned photoresist layerexposing the first conductive type substrate at the first side of thegate; performing an ion implantation process to form the secondconductive type first lightly doped region; and removing the patternedphotoresist layer.
 7. The manufacturing method as claimed in claim 1,further comprising forming a first conductive type lightly doped regionin the substrate at the second side of the gate, the first conductivetype lightly doped region being between the second conductive type drainregion and the gate.
 8. The manufacturing method as claimed in claim 7,wherein the step of forming the second conductive type first lightlydoped region in the first conductive type substrate at the first side ofthe gate and forming a first conductive type lightly doped region in thesubstrate at the second side of the gate comprises: forming a firstpatterned photoresist layer on the substrate, the first patternedphotoresist layer exposing the first conductive type substrate at thefirst side of the gate; performing a first ion implantation process toform the second conductive type first lightly doped region; removing thefirst patterned photoresist layer; forming a second patternedphotoresist layer on the substrate, the second patterned photoresistlayer exposing the first conductive type substrate at the second side ofthe gate; performing a second ion implantation process to form a firstconductive type lightly doped region; and removing the second patternedphotoresist layer.
 9. The manufacturing method as claimed in claim 7,further comprising forming a second conductive type second lightly dopedregion in the substrate at the second side of the gate, the secondconductive type second lightly doped region being between the secondconductive type drain region and the gate.
 10. The manufacturing methodas claimed in claim 9, wherein the step of forming the second conductivetype first lightly doped region and the second conductive type secondlightly doped region in the first conductive type substrate at the firstside and the second side of the gate and forming the first conductivetype lightly doped region in the substrate at the second side of thegate comprises: performing a first ion implantation process to form thesecond conductive type first lightly doped region and the secondconductive type second lightly doped region; forming a patternedphotoresist layer on the substrate, the patterned photoresist layerexposing the first conductive type substrate at the second side of thegate; performing a second ion implantation process to form the firstconductive type lightly doped region; and removing the patternedphotoresist layer.
 11. The manufacturing method as claimed in claim 1,wherein the step of forming the charge storage layer on the sidewall ofthe gate comprises: forming a charge storage material layer on the firstconductive type substrate; and performing an anisotropic etching processto remove part of the charge storage material layer.